1. Field of the Invention
The present invention relates to the field of electrically programmable and electrically erasable memory cells, and particularly to such memory cells with floating gates and a region having channel implants.
2. Description of the Background Art
Conventionally, metal-oxide-semiconductor (MOS) technology has been used to fabricate electrically programmable read-only memories (EPROMs) that employ floating gates, wherein polysilicon floating-gate members are completely surrounded by an insulator. During programming, electrical charge is transferred into the floating gate through a variety of mechanisms such as avalanche injection, channel hot electron injection, Fowler-Nordheim tunnelling, hot electron injection from the substrate, etc. A variety of phenomena have been used to remove charge including exposing the memory to ultraviolet radiation. Commercial EPROMs with floating gates first used avalanche injection to charge the floating gate; in second generation memories channel hot electron injection is used for programming. These memories are erased by exposure to ultraviolet radiation.
Electrically erasable and programmable read-only memories (EEPROMs) generally use a thin oxide region to tunnel charge into and from a floating gate or channel hot electrons to inject charge into a floating gate and then tunneling to extract the charge out of the floating gate. In a typical memory, a two transistor cell is used. See, for instance, U.S. Pat. No. 4,203,158 for a discussion of such cells and U.S. Pat. No. 4,266,283 for a discussion of related circuitry.
Other background references known to applicants are as follows.
U.S. Pat. No. 4,403,307, issued Sep. 6, 1983 to Maeda entitled SEMICONDUCTOR MEMORY DEVICE, discloses a semiconductor memory device composed of double gate type field effect transistors which have control gate and floating gate for accumulating charges. The conditions for optimum charge injection writing and for optimum reading of this semiconductor memory device are mutually inconsistent. In order to satisfy said two conditions, the reference invention provides a charge injection transistor and a read transistor, wherein the floating gate of both transistors are electrically connected, the control gates are connected to a first signal line, the drains are connected respectively to the different second and third signal lines and the sources are grounded.
This reference uses two separate MOSFETs, one with a high doped channel and the other with a low doped channel connected together so that the two FETs share the same floating and control gate and the same source.
U.S. Pat. No. 4,949,140, issued Aug. 14, 1990 to Tam entitled EEPROM CELL WITH INTEGRAL SELECT TRANSISTOR and U.S. Pat. No. 4,814,286, issued Mar. 21, 1989 to Tam entitled EEPROM CELL WITH INTEGRAL SELECT TRANSISTOR, discloses an electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the floating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.
U.S. Pat. No. 4,780,424, issued Oct. 25, 1988 to Holler et al entitled PROCESS FOR FABRICATING ELECTRICALLY ALTERABLE FLOATING GATE MEMORY DEVICES, discloses a process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines.
U.S. Pat. No. 4,622,656, issued Nov. 11, 1986 to Kamiya et al entitled NON-VOLATILE SEMICONDUCTOR MEMORY, relates to the reduction of programming voltage in a non-volatile memory of the type having a double gate structure composed of a select-gate and a floating gate. A channel region under the select-gate is highly doped and a channel region under the floating gate is lightly doped or doped to opposite conductivity type. Due to the different doping concentrations between these two channel regions, a large and steep surface potential gap appears at the transition region between the select-gate and the floating-gate in the programming operation thereby reducing the programming voltage.
U.S. Pat. No. 4,515,849, issued May 28, 1985 to Korsh et al entitled METHOD OF MAKING EPROM CELL WITH REDUCED PROGRAMMING VOLTAGE, discloses an improved floating gate MOS ESPROM cell which is programmable at a lower potential (12 volts) than prior art devices which require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.
U.S. Pat. No. 4,361,847, issued Nov. 30, 1982 to Harari entitled NON-VOLATILE EPROM WITH ENHANCED DRAIN OVERLAP FOR INCREASED EFFICIENCY, discloses a structure wherein the floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain.
U.S. Pat. No. 4,355,455, issued Oct. 26, 1982 to Boettcher entitled METHOD OF MANUFACTURE FOR SELF-ALIGNED FLOATING GATE MEMORY CELL, relates to a structure wherein a floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the field oxide. The cell may be manufactured by the following method: forming insulation such as silicon oxide over the substrate to serve as gate oxide; forming a conductor such as polysilicon over the insulation; etching the polysilicon to a patterned mask and using the mask to dissolve the unprotected oxide to leave a future floating gate of polysilicon overlaying and coextensive with the future channel region in the direction transverse to the source-to-drain region; overlaying insulation such as a further oxide and then overlaying a second conductor such as polysilicon, which is thus insulated from the floating gate; patterning this second polysilicon, which will serve as a control gate, with a photoresist mask to etch the second conductor to form a control gate, and to preferentially remove enough oxide to expose the unmasked portion of the future floating gate, and etching this unmasked portion.
U.S. Pat. No. 4,141,926, issued Mar. 6, 1979 to Morgan entitled SELF-ALIGNING DOUBLE POLYCRYSTALLINE SILICON ETCHING PROCESS, discloses a process for fabricating a double layer polycrystalline silicon structure for a metal-oxide-semiconductor (MOS) integrated circuit. The upper polycrystalline silicon layer, after being etched to form a predetermined pattern, is used as a masking member for etching the lower polycrystalline silicon layer, thereby assuring alignment between the layers. A selective etchant which discriminates between the silicon layers is employed.
U.S. Pat. No. 4,016,588, issued Apr. 5, 1977 to Ohya et al entitled NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, describes a non-volatile semiconductor memory device that includes a gate insulating film which has a relatively thin portion in the vicinity of one of the source and drain regions at which p-n junction breakdown is performed for carrier injection.
Japanese Patent 1-30 2770, issued May 8, 1982 to Omatao entitled SEMICONDUCTOR DEVICE, discloses a structure that includes a P+ type impurity diffusion region as a second impurity region having the same conductivity type as a semiconductor substrate and the impurity concentration higher than that of the substrate formed, so as to neighbor to the side part covered with the first gate oxide film of of a drain region constituting an EPROM memory transistor. The impurity concentration gradient between the drain region and the diffusion region becomes large, and the junction breakdown strength is decreased. The avalanche phenomenon more liable to occur than conventional examples. The number of electrons generated by the avalanche phenomenon increases, and the energy becomes large. Thereby, sufficient electron injection is enabled.
Japanese Patent 57-73978, issued May 8, 1982 to Yamada entitled SEMICONDUCTOR DEVICE, relates to means to accelerate the responding speed of a semiconductor device having a floating gate by forming a diffuse layer of higher impurity density than a substrate and of the same conductive type as the substrate under a field oxidized film in contact with the drain of the element, thereby lowering the writing voltage.
Japanese Patent 52-28777, issued Mar. 3, 1977 to Iizuka entitled NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, describes means to lower the voltage of writing and shorter time of writing by forming a P+ layer contacted with a drain region on the channel region of P type substrate.
European Patent 0046886, issued Aug. 29, 1980 to Siemens, discloses dynamic RAM single transistor memory cells production, integrated in semiconductor chip by forming oxide structures, e.g., by Locos process.
Canadian Patent 1119-299, issued Feb. 5, 1979 to Chan et al, discloses an inverse floating gate semiconductor EPROM that has a heavily doped P-type region within channel regions underlying laterally extending part of floating gate to accelerate electrons.
The device has a p-type substrate, N-type source and drain regions formed in the substrate. A channel region extends between the source and the drain, and a selection gate and gate are stacked above the channel region. The gates are electrically insulated from one another and from the channel region by oxide layers, the floating gate having a first part overlying the selection gate and a second part projecting laterally beyond the selection gate. The selection gate extends closer to the channel region than the first part.
A heavily doped p-type region is provided within the channel region and underlying the second part of the floating gate. The heavily doped p-type region acts in operation of the device, to accelerate electrons along the channel region, the heavily doped p-type region vertically defined at one edge by the drain. The device is fabricated on a silicon substrate and has polysilicon gates. A matrix of leads is provided for selecting individual devices.